1. Field
The present invention relates to a non-volatile memory device, a method for fabricating the same, and a method for fabricating a semiconductor device by using the same; and more particularly, to a non-volatile memory device having a split gate type cell structure, a method for fabricating the same and a method for fabricating a semiconductor device by using the same.
2. Description of Related Art
Generally, although an electric power is blocked, data stored in a memory cell of a non-volatile memory device is not damaged and thus, the non-volatile memory device has been widely used for a personal computer (PC) bias and for data storing of a set-top box, a printer and a network server. Recently, the non-volatile memory device has been used for a digital camera, a cellular phone and a smart card widely spread for public use.
A flash memory device and an electrical erasable programmable read only memory (EEPROM) device are widely used as a representative non-volatile memory device. A cell program operation of the EEPROM device is performed by using a hot electron injection method and an erasion operation is performed by using a fouler nordheim (F-N) tunneling method.
As for the hot electron injection method, a voltage is transferred to a cell drain and thus, a hot electron is formed in the drain side. Afterwards, a high voltage is transferred to a control gate, thereby injecting the hot electron formed in the drain side to a floating gate. Thus, a threshold voltage of the cell is increased. As for the F-N tunneling method, a high voltage is transferred to a source or a substrate and then, an electron injected to a floating gate by a program operation is discharged, thereby decreasing a threshold voltage of a cell.
A cell of the EEPROM device is divided as an electrically tunneling oxide (ETOX) cell of a simply stacked structure and a split gate type cell comprised of two transistors per a cell.
The ETOX cell is formed in a stacked structure of a floating gate for storing electric charges forming a gate and a control gate to which an operation power is transferred. Meanwhile, the split gate type cell uses a selection transistor and a cell transistor as one selection gate and is formed in a structure in which a predetermined portion of the selection gate is overlapped with a floating gate, and the remaining portion of the selection gate is placed on a substrate surface horizontally.
A cell size of the ETOX cell is very small compared with that of the split gate type cell and thus, the ETOX cell is more advantageous to a high integration. Since the ETOX cell uses the hot electron injection method during a program operation, there is an advantage a program current is very large. However, during the program operation and a read operation, interference between the cells is happened, and during an erasion operation, an excessive erasion is happened. Thus, there is a disadvantage in that an operation reliability of the device is degraded.
Meanwhile, the split gate type cell has a large cell size and accordingly, the split gate type cell is not suitable for a high integrated memory device. However, the split gate type cell has been widely used in a memory device in a semiconductor business due to good reliability of the split gate type cell during various operations. The split gate type cell hardly generates the excessive erasion problem because the selection transistor maintains a threshold voltage of the cell constantly. That is, after the erasion operation, although the floating gate shows a depletion property, a whole unit cell recognizes the threshold voltage of the selection transistor.
Accordingly, because of the above-described advantages of the split gate type cell, the split gate type cell has been widely used for the semiconductor devices. However, a channel length of the selection transistor of the spite gate type cell is determined by a lithography process, the channel length of the selection transistor may not be uniform according to an alignment technology of a lithography apparatus.
Accordingly, to solve the above limitations, the selection transistor of the split gate type cell is formed in a self-align method. That is, the split gate type cell having the selection transistor formed through the self-align method is conventionally suggested.
Hereinafter, with references to FIG. 1 and FIGS. 2A to 2I, a structure of the split gate type cell formed through the conventional self-align method and a method for fabricating the same will be briefly explained.
FIG. 1 is a top view illustrating a unit cell of a conventional self-aligned split gate type cell. FIGS. 2A to 2I are cross-sectional views illustrating a method for fabricating the conventional self-aligned split gate type cell. Herein, two split gate type cells operated in a pair, and a method for fabricating a semiconductor device in which a logic device is simultaneously formed is illustrated. Furthermore, a split gate type cell formed through FIGS. 2A to 2I is shown through the cross-sectional view taken along a line X-X′ shown in FIG. 1.
As shown in FIG. 1 and FIG. 2A, a device isolation layer 11 is formed in a substrate 10 and thus, a region which the split gate type cell will be formed (hereinafter, referred to as a cell region), and a logic region in which a logic device will be formed or a peripheral region (hereinafter referred to as a pen region) are defined.
Subsequently, as shown in FIG. 2B, a tunnel oxide layer 12 is formed on the substrate 10 provided with the device isolation layer 11. On the tunnel oxide layer 12, a first polysilicon layer 13 for a floating gate, an inter-poly dielectric (IPD) layer (not shown) and a hard mask layer 14 are sequentially deposited.
Subsequently, as shown in FIG. 2C, a mask process is performed and then, a first photoresist pattern 15 for forming a floating gate is formed on the hard mask layer 14.
Next, an etching process 16 is performed by using the first photoresist pattern 15 and thus, a first floating gate 17A and a second floating gate 17B (either of which is represented by a floating gate 17 as illustrated in FIG. 1) are formed on the substrate 10 of the cell region. Herein, reference numerals 12X, 13X and 14X denote the patterned tunnel oxide layers, the patterned first polysilicon layers, and the patterned hard mask layers.
Subsequently, as shown in FIG. 2D, a stripping process is employed, thereby removing the first photoresist pattern 15. Afterwards, an etching process 16 is employed and thus, the patterned hard mask layers 14× and the patterned IPD layer are removed.
Next, an insulation layer is deposited and then, a dry etching process is performed. Afterwards, a plurality of dielectric layers 18 is formed by using an inter-poly oxide layer to cover the first floating gate 17A and the second floating gate 17B, respectively.
Next, as shown in FIG. 2E, a gate insulation layer 19 is formed on an upper portion of the substrate 10. At this time, the gate insulation layer 19 can be formed in different thicknesses on the cell region and the pen region. For instance, a first gate insulation layer 19A is formed on the substrate 10 of both the cell region and the peripheral region. Afterwards, a photolithography process is employed, thereby removing the first gate insulation layer 19A existing on the substrate 10 of the pen region. Next, an oxide process is performed onto the substrate 10 of the peri region and thus, a second gate insulation layer 19B is formed in a different thickness from that of the first gate insulation layer 19A on the substrate 10 of the peri region.
Next, a second polysilicon layer 20 for a selection gate of the cell region or a gate electrode of the pen region is deposited over a height difference of an upper portion the structure provided with the gate insulation layer 19.
Next, as shown in FIG. 2F, a mask process is employed, thereby forming a second photoresist pattern 21 for forming a gate electrode of the pen region on the second polysilicon layer 20.
Next, an etching process 22 is performed by using the second photoresist pattern 21 as a mask and thus, the second polysilicon layer 20 and the second gate insulation layer 19B are etched. Accordingly, a peripheral gate electrode 23 of a transistor for a logic device is formed on the substrate 10 of the pen region. Herein, reference numerals 19B′ and 20′ denote the patterned second gate insulation layer and the patterned second polysilicon layer, respectively.
Next, as shown in FIG. 2G, through a stripping process, the second photoresist pattern 21 is removed. Afterwards, a mask process is performed and then, a third photoresist pattern 24 for forming a selection gate of the cell region is formed.
Next, an etching process 25 is performed by using the third photoresist pattern 24 as a mask, thereby forming a first selection gate 20A and a second selection gate 20B on an upper portion and sidewalls of the individual dielectric layer 18 to cover the dielectric layers 18 of the first floating gate 17A and the second floating gate 17B. At this time, the first selection gate 20A and the second selection gate 20B serve a role as a word line (WL). Herein, during the etching process 25, the first selection gate 20A and the second selection gate 20B are self-aligned on the sidewalls of the first floating gate 17A and the second floating gate 17B in a predetermined thickness. In addition, a reference numeral 19C denotes the patterned first gate insulation layers.
Next, as shown in FIG. 2H, through a stripping process, the third photoresist pattern 24 is removed.
Next, a lightly doped drain (LDD) ion impanation process is performed and thus, a plurality of LDD ion implantation regions 26 are formed in the substrate 10 in both sides of the first selection gate 20A, the second selection gate 20B and the peripheral gate electrode 23.
Next, a plurality of spacers 27 are formed on sidewalls of the first selection gate 20A, the second selection gate 20B and the peripheral gate electrode 23 by using an insulation layer.
Next, a source/drain ion implantation process is employed by using the spacers 27 as a mask and thus, a plurality of source/drain regions 28A and 28B are formed beside the LDD ion implantation regions, 26 exposed in both sides of the spacers 27 in a thickness deeper than that of the LDD ion implantation regions 26. Accordingly, two split gate type cells are formed on the substrate 10 of the cell region.
Next, a self-aligned silicide (SALICIDE) process is performed and then, a plurality of silicide layers 29 are formed on the first selection gate 20A and the second selection gate 20B, the source/drain regions 28A and 28B, and the peripheral gate electrode 23.
Next, as shown in FIG. 2I, on the resulting structure provided with the silicide layers 29, an inter-layer insulation layer 30 is deposited. Afterwards, an etching process is performed, thereby forming a plurality of contact holes (not shown) exposing the source/drain regions 28A and 28B.
Next, a plurality of contact plugs 31 (illustrated in FIGS. 1 and 2I) are formed by depositing a conductive layer (not shown) buried in the contact holes. Then, a photolithography process is performed, thereby forming a plurality of interconnection line layers on the contact plugs 31 by using the conductive layer.
That is, a first interconnection line layer 32A connected to the common source region 28A existing in the substrate 10 between the two split gate type cells, and a plurality of second interconnection line layers 32B individually connected to the drain regions 28B through the contact plugs 31 formed in one side of each of the two split gate type cells are formed. Furthermore, a third interconnection line layer 32C connected to the drain region 28B through the contact plug 31 of the peri region is formed. At this time, the first interconnection line layer 32A serves a role as a source line SL or a ground line, and the second interconnection line layer 32B serves a role as a bit line BL.
Meanwhile, FIG. 3 is a top view illustrating a conventional memory cell array fabricated through FIGS. 2A to 2I. As shown in FIG. 3, a bit line BL and a source line SL are placed in parallel with a minimum line width throughout a whole cell region in the conventional memory cell array. A reference denotation A denotes an active region.
However, the split gate type cell fabricated through the aforementioned methods shown in FIGS. 2A to 2I provides the following limitations. With reference to FIG. 4, these limitations will be explained.
First, during an etching process of a second polysilicon layer for a selection gate, polymer is generated and thus, a selection gate pattern formed on a cell region is damaged (refer to a reference denotation B of FIG. 4). The damaged gate pattern functions as a foreign body, thereby inducing defects in products.
Secondly, in case of performing an excessive etching process to remove the polymer, sidewalls of the selection gate is irregularly formed and thus, spacers are not formed on the sidewalls of the selection gate. Accordingly, the selection gate and the substrate are short-circuited due to a silicide layer formed through a subsequent process (refer to a reference denotation C of FIG. 4).
Thirdly, in case that the silicide layer is not formed to prevent the short-circuit between the selection gate and the substrate, a contact resistance of a source/drain region and that of the selection gate are increased. Meanwhile, to reduce the contact resistance, a contact size should be increased. The increase in the contact size increases a whole size of a semiconductor device.
Fourthly, since the selection gate is deposited on an upper portion of a floating gate, an overall height of a memory cell is increased. Accordingly, a tilt ion implantation process cannot be performed to form the source/drain region, and a degree of difficulty of a contact and interconnection process subsequently performed is increased due to the increased height of a contact plug. As a result, yields of products and reliability are reduced.
Fifthly, the selection gate can be formed through a self-aligned method; however, the selection gate and the floating gate can be misaligned due to a process change and a device condition (refer to a reference denotation D in FIG. 4). This misalignment is increased as a thickness of the selection gate gets thinner. Recently, according to a micronized trend of the semiconductor device, the thickness of the selection gate has been getting thinner. Accordingly, the misalignment has eventually increased and thus, a size of the selection gate is changed. Hence, there is limitation that a uniformity of the memory cell is degraded.
Sixthly, a contact hole and a metal inter connection line are formed in a minimum size during an interconnection line process. Accordingly, a bit line, to which a high voltage is transferred, and a grounded source line are placed in parallel with a minimum line width throughout a whole cell region. Thus, a coupling phenomenon is generated due to a parasitic capacitance between the bit line and the source line. Furthermore, the coupling phenomenon causes an interference phenomenon between the bit line and the source line. The interference phenomenon may not only induce a faulty operation of a semiconductor device, but or degrade a program operation speed and an erasion operation speed. In addition, the interference phenomenon increases a data access time.
Lastly, since the selection gate per unit cell is formed on sidewalls of the floating gate, a channel length of the unit cell is increased. Herein, the channel length is calculated by a mathematical formula of (a length of the floating gate+(a length of the selection gate×2)). Accordingly, a current amount flowing in a channel region is decreased. Particularly, according to the micronized trend of the semiconductor device, if a data accessing voltage is decreased, the current amount of the memory cell is abruptly decreased.